(originally posted here∞)

That old post didn't mention memory-mapped I/O controllers because I thought they only took up a couple MB. I'm not sure if the ability to hog a whopping 256MB + 512MB is something new to PCI Express or if I just overlooked it before.

Bottom line, Christian's post is right on -- it's a limitation of the chipset, and not one that's likely to change on Intel's midrange products. I/O devices need to map to the same address space that BIOS and Windows call "physical memory" in order to be compatible with PCI, and pushing parts of it over the 4GB boundary is expensive and cludgy. Until you go 64-bit, the best you can hope for is a BIOS option from someone like Abit to disable part of the theoretically required I/O address space. I have a feeling the number of peripherals that would stop working if you cut it from 768MB to more like 64MB is very small, given what I know about PCI and the fact that PCI-E is supposed to be compatible at the protocol level, but again I'm not too well read on the new stuff.

The /3g switch and other software-based ideas from the other thread definitely will not work. Incidentally, something I didn't clarify before is that applications have to be recompiled to support /3g, so even if you run into a situation where a process is running out of VM, the switch probably won't help. Even THEN, you have to be careful that crunching the kernel space into 1GB isn't going to make things worse -- Terminal Services is one app that does support /3g, yet when it runs out of memory it's often when the kernel is doing the bookkeeping for hundreds of client threads, not merely when the client apps are doing lots of paging. Basically it's one of those tiny features that's actually useful to maybe a dozen people worldwide, yet somehow makes it into enthusiast "XP Tweak guides." Bah. (no reflection on anyone here; the amount of misinformation on the net is staggering)

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